A power semiconductor device is a device that has such a high breakdown voltage as to draw large amounts of current from it and that is required to cause as low loss as possible. In the past, such power semiconductor devices used to be fabricated on a silicon (Si) substrate in most cases. Recently, however, power semiconductor devices with a silicon carbide (SiC) substrate have attracted a lot of attention and have been researched and developed extensively (see Patent Documents Nos. 1 to 6, for example).
As a semiconductor material, silicon carbide (SiC) has a dielectric breakdown strength that is one-digit higher than that of silicon (Si). That is why even if the thickness of a depletion layer is reduced at a pn junction or a Schottky junction, the SiC substrate can still maintain a sufficiently high avalanche breakdown voltage. For that reason, by using SiC, the device can not only have its overall thickness reduced but also be doped at a higher level as well. With these advantageous features, SiC is expected to be a promising material to make a power semiconductor device that has a low ON-state resistance and a high breakdown voltage and that would cause just low loss.
Patent Document No. 1 discloses a silicon carbide semiconductor device that can have increased ON-state resistance by increasing its channel mobility. FIG. 17 illustrates a silicon carbide semiconductor device of the type disclosed in Patent Document No. 1.
The silicon carbide semiconductor device 1000 shown in FIG. 17 is an n-channel planar-gate MOSFET (vertical power MOSFET) and includes an n+-SiC substrate 101. On the principal surface of the n+-SiC substrate 101, an n−-SiC epitaxial layer (which will be sometimes simply referred to herein as an “epi-layer”) 102 has been grown. And in predetermined regions at the surface of the n−-SiC epi-layer 102, a p-SiC base layer has been formed as well regions 103a and 103b to reach a predetermined depth. In the base layer 103a and 103b, n+-source regions 104a and 104b have been defined. And another thin epi-layer has been formed over the n−-SiC epi-layer 102 so as to contact with the n+-source regions 104a and 104b. Portions of that thin epi-layer (i.e., n+-regions 106a and 106b) form integral parts of the source regions 104a and 104b that are located right under them. Meanwhile, another portion of that thin epi-layer interposed between the source regions 104a and 104b has n−-type. And parts of the n−-region of that channel epi-layer 105 that are in contact with the p-base regions 103a and 103b function as channel regions 140.
Over the channel epi-layer 105, arranged is a gate electrode 108 with a gate oxide 107 sandwiched between them. The gate electrode 108 is covered with an insulating layer 109, on which a source electrode 110 is arranged so as to make electrical contact with the base regions 103a and 103b and the source regions 104a and 104b. And on the back surface of the SiC substrate 101, a drain electrode 111 has been formed.
In the semiconductor device 1000 shown in FIG. 17, when a voltage is applied to the gate electrode 108, a stored channel is induced in the channel epi-layer 105, thereby making carriers (charge) flow between the source electrode 110 and the drain electrode 111.
By operating a MOSFET in a storage mode in which a channel is induced without inverting the conductivity type of the channel forming layer in this manner, the channel mobility can be increased and the ON-state resistance can be reduced compared to a MOSFET of an inversion mode in which a channel is induced by inverting the conductivity type.    Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 10-308510    Patent Document No. 2: Japanese Patent Publication No. 3773489    Patent Document No. 3: Japanese Patent Publication No. 3784393    Patent Document No. 4: Japanese Patent Publication No. 3527496    Patent Document No. 5: Japanese Patent Application Laid-Open Publication No. 11-266017    Patent Document No. 6: Japanese Patent Application Laid-Open Publication No. 2008-098536